This invention relates to an electronic apparatus connected to and used with, for example, serial bus using an IEEE 1394 High performance a serial bus format, and more particularly to an electronic apparatus wherein the power dissipation of a communication interface is reduced.
A system is available wherein electronic apparatus such as a personal computer, a digital video cassette recorder and a digital television receiver are interconnected by an IEEE 1394 serial bus such that packets of a digital video signal, a digital audio signal and a control signal are communicated between the electronic apparatus.
FIG. 5 shows an example of a system of the type just described. Referring to FIG. 5, electronic apparatus A to C may be a personal computer, a digital video cassette recorder and some other electronic apparatus. Ports P of the electronic apparatus A and B and ports P of the electronic apparatus B and C are interconnected by IEEE 1394 serial bus cables 11 and 12, respectively. Such electronic apparatus are hereinafter referred to suitably as nodes.
Though not shown, each of the IEEE 1394 serial cables 11 and 12 has two pairs of twisted pair cables provided in the inside thereof. One pair of the two pairs of twisted pair cables is used for transmission of data, and the other pair is used for transmission of a strobe signal. Each node outputs a bias voltage to one of the two pairs of twisted pair cables and detects a bias voltage on the other pair of twisted pair cables.
As seen in FIG. 5, each node includes, as an interface (which may be hereinafter referred to suitably as 1394 interface) for performing communication via an IEEE 1394 serial bus, a physical layer controller (PHY) 13, a link layer controller (LINK) 14 and a CPU 15. The physical layer controller 13 is formed from an IC and has functions of initialization of a bus, encoding/decoding of transmission/reception data, bus arbitration, outputting/detection of a bias voltage and so forth. Meanwhile, the link layer controller 14 is formed from an IC and has link layer controlling functions such as production/detection of an error correction code, production/detection of a packet and so forth. Further, the CPU 15 is formed from a microcomputer and has a controlling function for an application and so forth.
In the communication system having the construction described above, if power supply to each of the nodes A to C is made available, then a power supply voltage is supplied to all of the physical layer controller 13, link layer controller 14 and CPU 15 of the node. Thereupon, the physical layer controller 13 of the node outputs a bias voltage to one of the two pairs of twisted pair cables of the IEEE 1394 serial bus 11. This bias voltage is detected by the physical layer controller of the other node connected thereto directly by the IEEE 1394 serial bus. As a result, each node detects that another node has been connected to the node itself.
If a bias voltage outputted from the physical layer controller of each node to the bus is detected by the physical layer controller of another node, then bus resetting takes place, and allocation of physical addresses to the individual nodes is automatically completed in a predetermined time. Then, after the allocation of physical addresses to the individual nodes is completed, the nodes A to C start transactions necessary upon bus resetting determined by a protocol.
In each of the nodes described above, when a power supply to the node is made available, a power supply voltage is supplied to all of the physical layer controller, link layer controller and CPU. Accordingly, when the node is not connected to any other node by a bus, wasteful power is dissipated by those blocks. Therefore, where the node is an apparatus which is driven by a battery such as a video cassette recorder integrated with a camera or the like, the continuously usable time of the apparatus is reduced.